...weiter zum Shop Sehr geehrter Kunde, Sie verlassen nun unseren Preisvergleich und werden in wenigen Sekunden zum Shop weitergeleitet. Für die dort angebotenen Produkte und Dienstleistungen wird keine Haftung übernommen. Falls Sie nicht weitergeleitet werden, bitte > hier < klicken! Paul G. A Jespers: The gm/ID Methodology, a sizing tool for low-voltage analog C The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuitsvon Paul G. A JespersJanuar 2010, Springer-Verlag GmbH, Audio CD, EAN 9780387471006BeschreibungIC designers appraise currently MOS transistor geometries and currents to compromise objectives like gain-bandwidth, slew-rate, dynamic range, noise, non-linear distortion, etc. Making optimal choices is a difficult task. How to minimize for instance the power consumption of an operational amplifier without too much penalty regarding area while keeping the gain-bandwidth unaffected in the same time? Moderate inversion yields high gains, but the concomitant area increase adds parasitics that restrict bandwidth. Which methodology to use in order to come across the best compromise(s)? Is synthesis a mixture of design experience combined with cut and tries or is it a constrained multivariate optimization problem, or a mixture? Optimization algorithms are attractive from a system perspective of course, but what about low-voltage low-power circuits, Vielen Dank |